Passivated magneto-resistive bit structure

ABSTRACT

A passivated magneto-resistive bit structure is disclosed in which surfaces subjects to oxidation or corrosion are protected. In one embodiment, a bit structure is encapsulated by means of an etch stop barrier material. In another embodiment an etch stop barrier material protects the top of a bit structure and dielectric spacers protect the side walls.

REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation application of U.S. patentapplication Ser. No. 10/078,234, filed on Feb. 14, 2002, entitled“PASSIVATED MAGNETO-RESISTIVE BIT STRUCTURE,” [with attorney docketMICRON.214C1], which is a continuation of U.S. patent application Ser.No. 09/638,419, filed Aug. 14, 2000, entitled“PASSIVATED-MAGNETO-RESISTIVE BIT STRUCTURE AND PASSIVATION METHODTHEREFOR,” now U.S. Pat. No. 6,392,922, issued on May 21, 2002, [WITHattorney docket MICRON.214A], the entireties of which are herebyincorporated by reference herein.

GOVERNMENT RIGHTS

[0002] This invention was made with Government support under ContractNumber MDA972-98-C-0021 awarded by DARPA. The Government has certainrights in this invention.

BACKGROUND OF THE INVENTION

[0003] The present invention relates to magneto-resistive memories, andmore particularly, to the passivation of magneto-resistive bitstructures.

[0004] Typical magneto-resistive memories such as giantmagneto-resistive random access memory cells (GMR MRAM's) use variationsin the magnetization direction of a thin film of ferromagnetic materialin a GMR stack can be referred to as a magneto-resistive bit. During awrite operation, the magnetization direction of a selected bit is set bypassing an appropriate current near the bit, often using a word line,digital line, or sense line. The current produces a magnetic field thatsets the magnetization direction of at least one of the layers in theferromagnetic film in a desired direction. The magnetization directiondictates the magneto-resistance of the film. During a subsequent readoperation, the magneto-resistance of the film can be read by passing asense current through the bit structure via a sense line or the like.

[0005] Some prior art magneto-resistive bit structures are shown anddescribed in U.S. Pat. No. 4,731,757 to Daughton et al. and U.S. Pat.No. 4,780,848 to Daughton et al., both of which are assigned to theassignee of the present invention and both of which are incorporatedherein by reference. Illustrative processes for forming such magneticbit structures are shown and described in U.S. Pat. No. 5,496,759 to Yueet al., and U.S. Pat. No. 5,569,617 to Yeh et al., both of which areassigned to the assignee of the present invention and both of which areincorporated herein by reference.

[0006] Such magneto-resistive memories are often conveniently providedon the surface of a monolithic integrated circuit to provide easyelectrical interconnection between the bit structures and the memoryoperating circuitry on the monolithic integrated circuit. To provide asense current through the bit structure, for example, the ends of thebit structure are typically connected to adjacent bit structures througha metal interconnect layer. The string of bit structures then forms asense line, which is often controlled by operating circuitry locatedelsewhere on the monolithic integrated circuit.

[0007] A problem which arises as a result of the use ofmagneto-resistive memories is that conventional integrated circuitprocesses often cannot be used to form the contact holes or vias thatare used to provide connections to the bit structure. For example, in aconventional integrated circuit process, vias are often formed by meansof an etching process. First, a patterned photoresist layer, whichdefines the location and size of the vias, is provided over theintegrated circuit. With the photoresist layer in place, vias are etcheddown to the bit structure. Once the vias are etched, a photoresistremoval step typically is used to remove the photoresist layer.

[0008] In a typical integrated circuit back-end process the GMR bit endsare susceptible to damage by the corrosive chemicals used in the etchingprocess. Furthermore, GMR bit ends may be exposed to a plasmaenvironment with oxygen during removal of the photoresist in the oxygenasher process and are left unpassivated thereafter. Oxidation of theside walls of the bit ends can lead to significant degradation andadversely affect performance of the GMR MRAM's. In order to avoidpotential disastrous consequences, oxygen plasma photoresist removal isnot generally utilized as the post Permalloy via etch or subsequent M3etch stages. Instead, various solvent photoresist strip process areutilized to remove the photoresist layers. Where a solvent or “wet”photoresist strip is used, it is necessary to choose the solvent withextreme care and to limit solvent use to mild solvents. In general, wetphotoresist strips, although reducing the risk of oxidation, are proneto other defects and are not very production-worthy.

[0009] What would be desirable, therefore, is a magneto-resistive bitstructure which is not subject to oxidation or corrosion by processingsteps when forming vias. More specifically, it would be desirable toform a magneto-resistive bit structure without directly exposing theside walls of the bit ends to the potentially adverse effects ofprocesses involved in via formation. This may allow more efficient andreliable back-end processing, which, in turn may reduce the defectdensity and increase the overall performance of devices incorporatingmagneto-resistive memories.

SUMMARY OF THE INVENTION

[0010] The present invention overcomes many of the disadvantages of theprior art by providing a magneto-resistive bit structure wherein thebits are protected from the potentially adverse effects of process stepsthat could damage the unprotected bit structure.

[0011] In one embodiment of the invention, magneto-resistive bits areencapsulated by means of an etch stop barrier material, such as CrSi,which is deposited as a barrier to cover both the top surface and sidewalls of a GMR stack. Encapsulation of GMR cells is highly desirable inthe switching characteristics of the cells. The etch stop barriermaterial, preferably CrSi, provides a good barrier to oxygen andcorrosive chemicals and thereby improves the robustness of GMR cells. Itis selected to have a bulk resistivity which is low enough to allowsense line contact and high enough so that shunting will be negligible.

[0012] In another embodiment of the present invention, an etch stopbarrier layer, for example, a layer of CrSi protects the top of the GMRstack while the side walls are protected by means of a dielectricextending along the edges of the GMR stack. For example, a SiN spacercan be formed by means of a controlled Permalloy via etch.

[0013] Metals deposited upon the passivated bit structure contact thebit ends only from the top through the etch stop layer, while the sidewalls of the bit ends are insulated from the metal by the dielectricspacer.

[0014] Passivation of magneto-resistive bit structures by the methods ofthis invention significantly improves the repeatability of GMR cells andmakes the GMR back-end process more production-worthy.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Other objects of the present invention and many of the attendantadvantages thereof will be readily appreciated as the same becomesbetter understood by reference to the following detailed descriptionwhen considered in connection with the accompanying drawings, in whichlike reference numerals designated like parts throughout the figuresthereof and wherein:

[0016]FIG. 1 is a plan view, partly in phantom, of one illustrativeembodiment of the passivated magneto-resistive bit structures of thepresent invention;

[0017]FIG. 2 is a plan view showing sense line metal contacts on top ofthe passivated magneto-resistive bit structure shown in FIG. 1;

[0018] FIGS. 3 to 10 are cross-sectional views showing certain of thesteps of a process for forming a passivated magneto-resistive bitstructure according to one embodiment of the present invention; and

[0019] FIGS. 11 to 15 are cross-sectional views showing certain of thesteps of a process for forming the passivated magneto-resistive bitstructure according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0020]FIG. 1 is a plan view of an illustrative embodiment of the presentinvention. An array of passivated magneto-resistive bit structures areshown generally at 2. A passivating material 4 is deposited on top ofmagneto-resistive bit 6, shown in phantom. FIG. 2 is similar to FIG. 1with sense line metal contacts 8 deposited on top of passivatingmaterial 4, which is at least partially conductive.

[0021] A process for forming a passivated magneto-resistive bitstructure according to a preferred embodiment of the present inventionwill now be illustrated by reference to FIGS. 3 to 10.

[0022] Referring to FIG. 3, a GMR stack 32 is shown deposited upon a SiNsubstrate 30, which may be a 500 Å SiN layer. Alternatively, substrate30 may be a monolithic integrated circuit or an integrated circuitseparated from GMR stack layer 32 by a dielectric layer. A SiN layer 34is deposited upon GMR stack 32. SiN layer 34 may be an 800 Å SiN layer.

[0023] In the next step of the process, an ion mill mask is built uponGMR stack 32 using the SiN layer 34. FIG. 4 shows ion mill mask 34 aformed from SiN layer 34. Part of SiN layer 34 is etched away byreactive ion etching.

[0024] In the next step of the process, ion milling is used to patternGMR stack 32. FIG. 5 shows a patterned GMR stack 32 a resulting fromthis step, in which ion mill mask 34 a is removed as well as part of GMRstack layer 32.

[0025] The next step in the overall process is the deposition of abarrier layer, which, after patterning, serves as the encapsulant inthis embodiment of the present invention. As a barrier layer any etchstop material can be used which has a bulk resistivity low enough toallow sense line contact and high enough so that shunting will benegligible. CrSi is preferred. If desired, a thin Ta or TaN diffusionbarrier can be deposited between the above-described barrier layer andthe GMR stack to prevent intermixing. FIG. 6 shows a barrier layer 36,made up of a 300 Å CrSi layer on a 100 Å Ta layer, deposited uponpatterned GMR stack 32 a and SiN substrate 30.

[0026] Following the TalCrSi barrier layer deposition a dielectric layeris deposited upon barrier layer 36. Any dielectric can be used. SiO₂ orSiN is preferred. FIG. 7 shows a 1000 Å SiO₂ layer 38 deposited uponTa/CrSi barrier layer 36.

[0027] Following deposition of SiO₂ layer 38, in the next step, shown inFIG. 8, a part of dielectric layer 38 is removed by reactive ion etch toexpose the unwanted portions of Ta/CrSi barrier layer 36, resulting inpatterned dielectric layer 38 a.

[0028] With the unwanted portions of the Ta/CrSi barrier layer 36exposed, ion milling is utilized to remove the unwanted portions of theTa/CrSi barrier layer 36. FIG. 9 shows pattern Ta/CrSi barrier layer 36a resulting from this step as well as a residual SiO₂ layer 38 b.Patterned SiO₂ layer 38 a in FIG. 8 has been reduced in thickness as aresult of the ion milling step to result in residual SiO₂ layer 38 bhaving a thickness of 400 Å.

[0029] Finally, as shown in FIG. 10 residual SiO₂ layer 38 b from FIG. 9is removed by reactive ion etch, resulting in GMR stack 32 a being fullyencapsulated by Ta/CrSi barrier 36 a. Thus, a passivatedmagneto-resistive bit structure is provided by encapsulation of the GMRstack by means of a Ta/CrSi barrier. Both the tops and the side walls ofthe GMR bits are protected by passivation in the manner described above.The side walls of the GMR bits are not exposed either during Permalloyvia etch or thereafter. Therefore, oxygen asher photoresist removal andconventional wet chemical strips can be used without damage to thepassivated GMR bits.

[0030] An alternative embodiment of the present invention will now beillustrated in reference to FIGS. 11 to 15. Referring to FIG. 11, anunderlayer 40, which may be a monolithic integrated circuit, serves as asubstrate for a GMR stack 42. Underlayer 40 preferably includes adielectric layer separating the GMR stack from an integrated circuit.The dielectric layer may be, for example, a 500 Å seed SiN layer, notshown. A CrSi barrier layer 44 is deposited on top of GMR stack 42. ASiN ion mill mask 46 is fabricated in a known manner on top of CrSilayer 44. For example, a relatively thick SiN layer can be depositedupon CrSi layer 44 and patterned using a photoresist and reactive ionetch. Layer 44 may, for example, be an 800 Å thick CrSi layer. CrSi ispreferred because, in addition to being a good oxygen barrier and etchstop, CrSi has a bulk resistivity low enough to allow sense line contactand high enough to minimize shunting. Ion mill mask 46 may be a 2000 ÅSiN layer. Other suitable dielectric materials such as SiO₂ can be used,if desired. SiN is preferred because, in addition to being an excellentdielectric, it provides an efficient barrier against oxidation andprotects GMR bits from other damaging materials as well.

[0031] The next steps in the process is illustrated in FIG. 12, whereinthe results of ion milling are shown. It can be seen that portions ofCrSi layer 44 and portions of GMR stack 42 have been removed, resultingin patterned GMR stack 42 a and patterned CrSi barrier layer 44 a. Theion mill mask is then separately removed. As shown, CrSi layer 44 a hasbeen reduced from a thickness of 800 Å to a remaining thickness of 700Å.

[0032] The next step in the process is deposition of a layer of adielectric material, such as a 2000 Å layer of SiN or SiO₂, followed byplanarization, such as by using high angle ion milling or chemicalmechanical polishing (CMP). FIG. 13 shows a planarized layer of SiN 48deposited upon the structure of FIG. 12.

[0033] The next process step is a controlled Permalloy via etch, theresults of which are illustrated in FIG. 14. In this step most of theSiN layer 48 is removed, leaving naturally created SiN passivationspacers 48 a along the side walls 42 b of patterned GMR stack 42 a andproviding a passivated magneto-resistive bit structure. Spacers 48 a areshown abutting the side walls 42 b of patterned GMR stack 42 a and theside walls 44 b of patterned CrSi layer 44 a. Spacers 48 a are shownhaving side walls 48 b, which are spaced out laterally from the sidewalls 42 b of GMR stack 42 a and side walls 44 b of patterned CrSi layer44 a.

[0034] In FIG. 15 a contact metal 50 is deposited over the passivatedmagneto-resistive bit structure of FIG. 14. Contact metal 50 does notcontact GMR stack 42 a directly at any point, since the side walls 42 bof GMR stack 42 a are protected by spacers 48 a and the top of GMR stack42 a is protected by CrSi layer 44 a. Indirect contact between GMR stack42 a and contact meal 50 is possible only at the top of GMR stack 42 athrough CrSi layer 44 a, which conducts electric current between contactmetal 50 and GMR stack 42 a. The SiN spacers provide an excellentbarrier against oxidation and contact by corrosive chemicals.

[0035] Having thus described the preferred embodiments of the presentinvention, those of skill in the art will readily appreciate that yetother embodiments may be made and used within the scope of the claimshereto attached. Numerous advantageous of the invention covered by thisdocument have been set forth in the foregoing description. It will beunderstood, however, that this disclosure is, in many respects, onlyillustrative. Changes may be made in details, particularly in matters ofshape, size, and arrangement of parts without exceeding the scope of theinvention.

We claim:
 1. A passivated magneto-resistive bit structure, comprising: amagneto-resistive bit having a top surface and side walls; a conductiveetch stop barrier layer encapsulating the top surface and side walls ofsaid bit; and a metal contact provided upon at least part of said etchstop barrier layer.
 2. The bit structure of claim 1, wherein said etchstop barrier layer comprises CrSi.
 3. The bit structure of claim 2,wherein said etch stop barrier layer further comprises Ta.
 4. The bitstructure of claim 1, wherein said etch stop barrier layer includes adiffusion barrier.
 5. The bit structure of claim 1, further comprising adiffusion barrier between said etch stop barrier layer and said bit. 6.The bit structure of claim 5, wherein said diffusion barrier comprises amaterial selected from the group consisting of Ta and TaN.